Current Issue : January - March Volume : 2014 Issue Number : 1 Articles : 5 Articles
The intrinsic variability of nanoscale VLSI technology must be taken into account when analyzing circuit designs to predict\r\nlikely yield. Monte-Carlo- (MC-) and quasi-MC- (QMC-) based statistical techniques do this by analysing many randomised or\r\nquasirandomised copies of circuits. The randomisation must model forms of variability that occur in nano-CMOS technology,\r\nincluding ââ?¬Å?atomisticââ?¬Â effects without intradie correlation and effects with intradie correlation between neighbouring devices.\r\nA major problem is the computational cost of carrying out sufficient analyses to produce statistically reliable results. The use\r\nof principal components analysis, behavioural modeling, and an implementation of ââ?¬Å?Statistical Blockadeââ?¬Â (SB) is shown to be\r\ncapable of achieving significant reduction in the computational costs. A computation time reduction of 98.7% was achieved for\r\na commonly used asynchronous circuit element. Replacing MC by QMC analysis can achieve further computation reduction,\r\nand this is illustrated for more complex circuits, with the results being compared with those of transistor-level simulations. The\r\nââ?¬Å?yield predictionââ?¬Â analysis of SRAM arrays is taken as a case study, where the arrays contain up to 1536 transistors modelled using\r\nparameters appropriate to 35 nm technology. It is reported that savings of up to 99.85% in computation time were obtained....
The existence of structural, control, and data hazards presents a major challenge in designing an advanced pipeline/superscalar\r\nmicroprocessor. An efficient memory hierarchy cache-RAM-Disk design greatly enhances the microprocessor�s performance.\r\nHowever, there are complex relationships among the memory hierarchy and the functional units in the microprocessor. Most\r\npast architectural design simulations focus on the instruction hazard detection/prevention scheme from the viewpoint of function\r\nunits. This paper emphasizes that additional inboard memory can be well utilized to handle the hazardous conditions. When the\r\ninstruction meets hazardous issues, the memory latency can be utilized to prevent performance degradation due to the hazard\r\nprevention mechanism. By using the proposed technique, a better architectural design can be rapidly validated by an FPGA at the\r\nstart of the design stage. In this paper, the simulation results prove that our proposed methodology has a better performance and\r\nless power consumption compared to the conventional hazard prevention technique....
Due to the ever-growing requirements in high performance data computation, multiprocessor systems have been proposed\r\nto solve the bottlenecks in uniprocessor systems. Developing efficient multiprocessor systems requires effective exploration of\r\ndesign choices like application scheduling, mapping, and architecture design. Also, fault tolerance in multiprocessors needs to\r\nbe addressed. With the advent of nanometer-process technology for chip manufacturing, realization of multiprocessors on SoC\r\n(MpSoC) is an active field of research. Developing efficient low power, fault-tolerant task scheduling, and mapping techniques\r\nforMpSoCs require optimized algorithms that consider the various scenarios inherent in multiprocessor environments. Therefore\r\nthere exists a need to develop a simulation framework to explore and evaluate new algorithms on multiprocessor systems. This\r\nwork proposes amodular framework for the exploration and evaluation of various design algorithms forMpSoC system.This work\r\nalso proposes new multiprocessor task scheduling and mapping algorithms for MpSoCs. These algorithms are evaluated using\r\nthe developed simulation framework. The paper also proposes a dynamic fault-tolerant (FT) scheduling and mapping algorithm\r\nfor robust application processing. The proposed algorithms consider optimizing the power as one of the design constraints. The\r\nframework for a heterogeneous multiprocessor simulation was developed using SystemC/C++ language. Various design variations\r\nwere implemented and evaluated using standard task graphs. Performance evaluation metrics are evaluated and discussed for\r\nvarious design scenarios....
Now a day’s mobiles are replacing the use of laptops and desktops on large scales. The mobile Operating system companies provide more resources for the creation of applications as per the user’s requirement. But due the use of various operating system, it becomes problem for developer to develop the application for each operating system individually. So this has been solved by the cross platform mobile application development tool which provides more scope in less time. This paper describes a mobile hardware/software system to help with screening of skin diseases. Our system uses an inexpensive apparatus (microscope) and a Smartphone. These two components standalone are sufficient to capture highly detailed images for use by experts with medical background. Our main goal is to demonstrate how Smartphone’s can turn into powerful and intelligent machines and help large populations without expertise in low-resource settings....
This work presents a method for global routing (GR) to minimize power associated with global nets.We consider routing in designs\r\nwith multiple supply voltages. Level converters are added to nets that connect driver cells to sink cells of higher supply voltage and\r\nare modeled as additional terminals of the nets during GR. Given an initial GR solution obtained with the objective of minimizing\r\nwirelength, we propose a GR method to detour nets to further save the power of global nets.When detouring routes via this procedure,\r\noverflow is not increased, and the increase in wirelength is bounded. The power saving opportunities include (1) reducing\r\nthe area capacitance of the routes by detouring fromthe higher metal layers to the lower ones, (2) reducing the coupling capacitance\r\nbetween adjacent routes by distributing the congestion, and (3) considering different power weights for each segment of a routed\r\nnet with level converters (to capture its corresponding supply voltage and activity factor).We present a mathematical formulation\r\nto capture these power saving opportunities and solve it using integer programming techniques. In our simulations, we show\r\nconsiderable saving in a power metric for GR, without any wirelength degradation....
Loading....